IEEE

SVM-Based Framework is Designed for Precise On-Chip Power Analysis in CMOS VLSI Circuits

Abstract: Power analysis plays a crucial role in ensuring the reliability of very -large-scale integration (VLSI) circuits. Accurate power analysis is essential during the early stages of the design ...
IEEE

Energy-Efficient and High-Speed Shift Registers for Sustainable VLSI Using Tri-Mode Multi-Threshold CMOS

Abstract: In this work, an optimized shift register architecture leveraging the Tri-Mode (Power-Gated) Multi-Threshold CMOS (MTCMOS) technique is proposed to reduce power consumption and delay while ...
Compoundsemiconductor.net

USTC team develops GaN/diamond CMOS power circuit

Well-matched normally-off diamond p-FET (2DHG) and GaN n-FET (2DEG) enable high-frequency and high-reliability CMOS power circuit Researchers from the University of Science and Technology of China ...
GitHub

rishit2003/CMOS-Full-Adder-VLSI-Design

This project implements a 1-bit NAND-based full adder in 180 nm CMOS, including schematic design, layout, DRC/LVS, parasitic extraction (Calibre PEX), and post-layout simulation. The design is built ...