EDN

SPICE-based stochastic design of SRAM Array considering PVT variations

Seeking an internship position during the summer of 2011 in the area of Digital ASIC Design with focus on Front-end design, Verification or Layout. Obtained Bachelor’s degree in Electronics ...
Nature

Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors

Memory technologies are fundamental to the performance and efficiency of computing systems. Among the various types of memory, static random-access memory (SRAM) and dynamic random-access memory (DRAM ...
Design-Reuse

A 55-nm Ultra Low Leakage SRAM Compiler with Optimized Power Gating Design

In this paper an optimized power gating design on a 55-nm Static Random Access Memory (SRAM) compiler is presented. Two low leakage modes: retention and sleep mode are discussed. The arrangement of ...
Electronic Design

Should Dual Rail Go Mainstream in Deep Nanometer Era?

Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the ...