EDN

MEMORIES: 1T SRAM for the masses

Fremont, Calif. — Even as design reuse evolves, taking much of the pain out of system-on-chip design for smaller design teams, embedded memory remains a problem. There are competent SRAM compilers for ...
Nature

One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors

In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory ...
Design-Reuse

sureCore Delivers Customised Low Power SRAM for Data Intensive Designs

SHEFFIELD, England, Mar. 21, 2019 – sureCore Limited's new SureFit SRAM customization service has delivered low power high capacity SRAM subsystems implemented in advanced FinFET processes to Tier-1 ...
Nature

Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors

Memory technologies are fundamental to the performance and efficiency of computing systems. Among the various types of memory, static random-access memory (SRAM) and dynamic random-access memory (DRAM ...
Semiconductor Engineering

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches

New academic paper titled “Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution”, from researchers at Univ.
Semiconductor Engineering

Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh Environments

On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is ...
Design-Reuse

1T-SRAM improves yield, benefits SoCs

Embedded memory has become essential for achieving greater bandwidth and faster processing in SoC designs at 0.13 µm and below. By eliminating off-chip delays and reducing system size, embedded memory ...
Electronic Design

Should Dual Rail Go Mainstream in Deep Nanometer Era?

Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the ...