Until recently, signal integrity has been a concern relegated predominantly to multi-gigabit serial interface design. Today, it is an aspect of design that engineers building high-speed parallel ...

The primary constraint has shifted: it is no longer front-end lithography only, but the packaging process itself. Reaching ...

The present trends in technology — such as increasing demand for computational power from CPUs and GPUs, connectivity driven by Internet of Things (IoT), data demands around connected and self-driving ...

The most different aspect between a normal lamination structure and High-Density Fan-out (HDFO) is the routing scale. That aspect is also the challenge and focus of this study. At an HDFO scale, most ...

As every engineer learns at an early stage, clock edges must be obeyed. In the digital domain, synchronization through global and local clock trees, slew rate and rising/falling times all combine to ...

Samsung has developed a new chip packaging technology that could significantly improve the speed and power-efficiency of semiconductor chips. The new Interposer-Cube4 (I-Cube4) technology is the ...

No gadget in this episode, I thought instead I’d write about a book I purchased recently. It is Eric Bogatin’s “Signal and Power Integrity — Simplified” second edition. Like most of you, I’ve got a ...

For system-on-a-chip designs at 90 and 65 nm, dynamic noise greatly exacerbates the challenge of timing signoff. To accurately examine noise effects, designers need tools that provide an accurate ...

For many years, power systems could be easily boiled down to a discussion of volts and amps. But for the past decade, the move to higher operating frequencies has brought another wrinkle to the power ...