Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex ...

As more system-on-chip (SoC) engineers rely on re-use to cut design time and reduce risk, the demand for synthesizable cores and other forms of intellectual property (IP) continues to rise ...

UVM testbenches for blocks are adequate until the stage of a subsystem with one or more processors. The new generation of constrained-random test cases based on scenario models can take it from there.

Verifying the integration and operation of new IP in a legacy system-on-a-chip (SoC) becomes challenging. This is true particularly when the legacy SoC environment was built using a directed test ...

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...

Questa provides our students with the capabilities needed as they learn to take full advantage of power of SystemVerilog for design and verification. The Questa graphical user interface is easy to ...

Semiconductor Engineering sat down to discuss the state of the industry for functional verification. The inability of RTL simulation to keep up with verification needs is causing rapid change in the ...

Constrained random verification (CRV) and formal verification are currently the state-of-the-art approaches to functional verification. CRV's advantage is that does not suffer from size restrictions.